How to write a VLSI fresher resume that gets shortlisted
A practical, India-focused guide for ECE freshers applying to RTL, verification, physical design, DFT, analog and embedded roles: what to write, what to leave out, and a sample you can copy.
The 5 rules that matter most
- One page, one column, PDF. No tables, text boxes, icons, skill bars or photos. Applicant tracking systems (ATS) read plain text best, and so do tired recruiters.
- Projects are your experience. For a fresher, 2–4 real projects with GitHub links matter more than anything else on the page.
- Every bullet shows what you built and how well it works. Use numbers: frequency, coverage, slack, area, errors fixed, time saved.
- Only write what you can defend. Interviewers pick any word on your resume and ask about it. One honest skill beats five you cannot explain.
- One resume per role. Keep a DV version, an RTL version and so on, and match the words in the job post (if it says “SystemVerilog Assertions”, write that, not just “SVA”).
Section by section (in this order)
1. Header
Name, city, phone, a professional email, LinkedIn, GitHub. That's it. No photo, date of birth, address, father's name or marital status.
2. Summary (2 lines)
Say the role you want and your strongest proof. “B.E. ECE 2026, aiming for DV. Built UVM testbenches for APB and UART with 95%+ coverage.” Skip generic objectives like “seeking a challenging position”.
3. Education
Degree, college, CGPA and years. One line each for Class XII and X with percentages (many Indian drives filter on these). Add M.Tech/PG diploma if you have one.
4. Technical skills
Group them: Languages, Verification/Design methods, Tools, Concepts. 4–6 lines. No “basic knowledge of”, no skill-level bars.
5. Projects
Your most important section. Name, tools, GitHub link, then 2–3 bullets with numbers. Put the project closest to the target role first.
6. Internships / training
Real internships first. Institute courses go under “Training”, described by what you built, not by the course name.
7. Achievements (optional)
Hackathons, tape-out contests, papers, GATE score, open-source contributions, leading a technical club. Skip school-level and unrelated items.
How to write a strong bullet
Action verb + what you built + with what + result (a number)
Worked on UART project using Verilog.
Designed a UART (8N1, 9600–115200 baud) in Verilog with a self-checking testbench; tested on a Basys-3 FPGA with a USB-serial link.
Did physical design of RISC-V using OpenLane.
Took a RISC-V core from RTL to GDSII with OpenLane (SKY130): 0 DRC/LVS errors, +0.42 ns worst setup slack at 50 MHz.
Good verbs: designed, built, verified, implemented, debugged, automated, reduced, optimized, closed (timing/coverage), wrote, integrated.
Role-wise tips
Pick your target role to see the keywords, sample bullets and projects that work best.
RTL / Digital design
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
Verilog, SystemVerilog (design), FSMs, pipelining, FIFOs, clock domain crossing (CDC), synthesis basics, STA basics (setup/hold), linting, AMBA AXI/APB, Xilinx Vivado or Intel Quartus, Yosys, Icarus/Verilator, GTKWave, Python or TCL
Strong project bullets (copy the pattern, use your own numbers):
- Designed a 4-stage pipelined RISC-V (RV32I) core in Verilog; passed 40+ instruction tests and ran at 100 MHz on an Artix-7 FPGA.
- Built an asynchronous FIFO with Gray-code pointers and 2-flop synchronizers for a 50 MHz → 125 MHz crossing; checked full/empty in simulation.
- Wrote an APB slave with 8 registers and a self-checking testbench; synthesized with Yosys and fixed all lint warnings.
Weak: “Designed a processor using Verilog.” – says nothing about what you built or how well it works.
Projects that impress for this role: RISC-V or MIPS core (single-cycle, then pipelined) · Async FIFO + CDC · UART / SPI / I2C controller · AXI-Lite or APB slave · FSM-based traffic or vending controller (only as a first project).
Full RTL / Digital design roadmap → Practise the interview questions →
Design verification (DV)
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
SystemVerilog (classes, constraints, interfaces), UVM (agents, sequences, scoreboard, RAL basics), functional coverage, SVA assertions, constrained-random testing, Python, Questa/VCS/Xcelium or EDA Playground, Git
Strong project bullets (copy the pattern, use your own numbers):
- Built a UVM testbench (agent, sequencer, driver, monitor, scoreboard) for an APB slave; reached 96% functional coverage with 12 constrained-random sequences.
- Wrote 15 SVA assertions for a FIFO (no overflow/underflow, ordering) and found 2 bugs in the design's full-flag logic.
- Verified a UART TX/RX at 3 baud rates with a reference model; automated regressions with a Python script.
Weak: “Knowledge of UVM and SystemVerilog.” – says nothing about what you built or how well it works.
Projects that impress for this role: UVM testbench for APB/AXI-Lite or UART · SVA + coverage for an async FIFO · Constrained-random test of an ALU with a reference model · RAL model for a small register block.
Full Design verification (DV) roadmap → Practise the interview questions →
Physical design (PD) / STA
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
RTL-to-GDSII flow, floorplanning, placement, CTS, routing, STA (setup/hold, OCV, SDC), DRC/LVS, IR drop basics, OpenLane/OpenROAD, SKY130 PDK, KLayout/Magic, TCL, Python, Linux
Strong project bullets (copy the pattern, use your own numbers):
- Took a 32-bit RISC-V core from RTL to GDSII with OpenLane on SKY130: 0 DRC/LVS errors, worst setup slack +0.42 ns at 50 MHz.
- Reduced routing congestion by changing core utilization from 60% to 45% and macro placement; compared the results in a short report.
- Wrote SDC constraints (clocks, I/O delays, false paths) and fixed 3 hold violations after CTS.
Weak: “Done physical design of a chip.” – says nothing about what you built or how well it works.
Projects that impress for this role: OpenLane run of a small design with your own SDC · Timing-closure experiment (clock period sweep) · Floorplan/utilization study with congestion maps · Power grid / IR drop comparison.
Full Physical design (PD) / STA roadmap → Practise the interview questions →
DFT (design for test)
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
Scan insertion, ATPG, fault models (stuck-at, transition), fault coverage, MBIST, JTAG/boundary scan, scan compression basics, Verilog, STA basics, TCL/Python
Strong project bullets (copy the pattern, use your own numbers):
- Inserted a scan chain into a 32-flop counter design and shifted/captured test patterns in simulation.
- Implemented a March C- MBIST controller for a 1 KB RAM in Verilog; injected stuck-at faults and detected all of them.
- Wrote a JTAG TAP controller (16-state FSM) with IDCODE and BYPASS and a testbench.
Weak: “Familiar with DFT concepts.” – says nothing about what you built or how well it works.
Projects that impress for this role: Scan chain on a small design · March C- MBIST controller · JTAG TAP controller · Hand fault-coverage calculation for a small circuit.
Full DFT (design for test) roadmap → Practise the interview questions →
Analog design / Layout
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
MOSFET operation, small-signal models, current mirrors, op-amp design, bandgap, LDO basics, SPICE (ngspice/Spectre), PVT corners, Monte Carlo, layout: matching, common-centroid, guard rings, DRC/LVS, Cadence Virtuoso or Magic/KLayout, SKY130
Strong project bullets (copy the pattern, use your own numbers):
- Designed a two-stage op-amp in SKY130: 62 dB gain, 25 MHz unity-gain bandwidth, 63° phase margin across 5 PVT corners (ngspice).
- Laid out a differential pair with common-centroid matching and guard rings in Magic; DRC- and LVS-clean.
- Compared pre- and post-layout simulation; extracted parasitics reduced bandwidth by 12%.
Weak: “Good knowledge of analog circuits.” – says nothing about what you built or how well it works.
Projects that impress for this role: Two-stage op-amp with compensation · Bandgap reference across temperature · Common-centroid layout of a diff pair · Pre- vs post-layout comparison.
Full Analog design / Layout roadmap → Practise the interview questions →
Embedded / Firmware / Validation
Keywords recruiters and ATS look for (add only the ones you can answer questions on):
Embedded C, pointers and bit manipulation, ARM Cortex-M (STM32), ESP32, interrupts, timers, DMA, UART/SPI/I2C, FreeRTOS, bare-metal drivers, logic analyser, oscilloscope, Python test automation, Git, Linux
Strong project bullets (copy the pattern, use your own numbers):
- Wrote a bare-metal I2C driver for an STM32F4 to read a BME280 sensor at 10 Hz; verified the bus timing on a logic analyser.
- Built a FreeRTOS data logger with 3 tasks (sense, process, log) using queues and a mutex; ran 48 hours without a crash.
- Automated board tests with Python and a USB serial link, cutting manual test time from 20 minutes to 3 minutes.
Weak: “Worked on Arduino projects.” – says nothing about what you built or how well it works.
Projects that impress for this role: Bare-metal STM32 driver (I2C/SPI) · FreeRTOS multi-task logger · Low-power ESP32 sensor node with measured battery life · Python test automation for a board.
Full Embedded / Firmware / Validation roadmap → Practise the interview questions →
Sample one-page resume (DV fresher)
This is what a clean, ATS-friendly fresher resume looks like. Copy the plain-text version below into Google Docs or Word and replace everything with your own details.
Summary
B.E. ECE graduate (2026) aiming for a Design Verification role. Built UVM testbenches for APB and UART with coverage-driven verification; comfortable with SystemVerilog, SVA and Python automation.
Education
Technical skills
Languages: Verilog, SystemVerilog, C, Python
Verification: UVM, SVA, functional coverage, constrained-random
Tools: Questa (EDA Playground), Icarus, GTKWave, Git, Linux
Concepts: FSMs, FIFOs, CDC basics, AMBA APB/AXI-Lite
Projects
- Built agent, sequencer, driver, monitor and scoreboard for an 8-register APB slave; 12 constrained-random sequences.
- Reached 96% functional coverage; found and fixed 2 bugs in address decode.
- 16-deep async FIFO with Gray-code pointers and 2-flop synchronizers.
- 15 SVA checks for overflow, underflow and ordering; all passing.
Training
Achievements
- Finalist, <Hackathon> 2025 (team of 3, FPGA design)
- GATE 2026 (EC) qualified
Sample with made-up details. Replace everything in <angle brackets> and every number with your own real work.
YOUR NAME Bengaluru, Karnataka · +91 98XXX XXXXX · [email protected] linkedin.com/in/yourname · github.com/yourname SUMMARY B.E. ECE graduate (2026) aiming for a Design Verification role. Built UVM testbenches for APB and UART with coverage-driven verification; comfortable with SystemVerilog, SVA and Python automation. EDUCATION B.E., Electronics and Communication Engineering 2022 – 2026 <College name>, <University> · CGPA 8.4/10 Class XII (PCM), <Board> · 89% 2022 Class X, <Board> · 92% 2020 TECHNICAL SKILLS Languages: Verilog, SystemVerilog, C, Python Verification: UVM, SVA, functional coverage, constrained-random testing Tools: Questa (EDA Playground), Icarus Verilog, GTKWave, Git, Linux Concepts: Digital design, FSMs, FIFOs, CDC basics, AMBA APB/AXI-Lite PROJECTS UVM Testbench for an APB Slave · SystemVerilog, UVM github.com/... - Built agent, sequencer, driver, monitor and scoreboard for an 8-register APB slave; 12 constrained-random sequences. - Reached 96% functional coverage; found and fixed 2 bugs in address decode. Asynchronous FIFO with Assertions · Verilog, SVA github.com/... - Designed a 16-deep async FIFO (Gray-code pointers, 2-flop synchronizers). - Wrote 15 SVA checks for overflow, underflow and ordering; all passing. INTERNSHIP / TRAINING VLSI Verification Training, <Institute> Jan – Jun 2026 - Completed 6 lab assignments on SV and UVM; final project above. ACHIEVEMENTS - Finalist, <Hackathon name> 2025 (team of 3, FPGA-based design) - GATE 2026 (EC) qualified, score 512
Common mistakes that get resumes rejected
- Two or three pages with course lists, school activities and hobbies.
- Listing tools you have only seen in a demo (PrimeTime, Innovus, Calibre…) and then failing basic questions on them.
- “Basic knowledge of C, C++, Java, Python, MATLAB, Verilog…” – a long list says you know none of them well.
- No GitHub links, or GitHub repos with no README, no results and no testbench.
- The same project as 200 other applicants (traffic light, 4-bit ALU) with no extra depth. Add pipelining, assertions, coverage or an FPGA demo to stand out.
- Wrong tool or term spelling: “System verilog”, “UVM methodolgy”, “cadance”. Recruiters notice.
- Unprofessional email or a file named resume_final_new2.pdf. Use YourName_DV_Resume.pdf.
- Calling an institute course an “internship” when it was paid training. Be accurate.
Checklist before you click Apply
Questions freshers ask
Should a VLSI fresher resume be one page?
Yes. Recruiters spend well under a minute on a first look, and a fresher rarely has enough real work to fill two pages. One clean page with 2–4 strong projects beats two pages of course names.
Should I add my 10th and 12th marks?
In India, yes, keep one line for each. Many campus and off-campus drives filter on 10th/12th percentages and CGPA cut-offs (often 60–70%, sometimes higher). Leaving them out can get you filtered out.
My CGPA is low. Should I hide it?
If a job asks for it, you will be asked anyway. Keep it, and let strong projects, a GitHub link and a good interview do the work. Apply where the stated cut-off fits you, and use referrals.
Should I add a photo, date of birth, father's name or religion?
No. They are not needed for engineering jobs, take space, and can invite bias. Name, city, phone, email, LinkedIn and GitHub are enough.
Can I write a training-institute course as an internship?
Only if it really was an internship with a company. Otherwise list it under “Training” and describe what you built. Interviewers check this, and a mismatch hurts trust.
Should I list every EDA tool I have heard of?
No. List only tools you have actually used and can talk about. Writing “Synopsys VCS, PrimeTime, Innovus, Calibre” after one demo invites hard questions you cannot answer.
Word or PDF?
Send a PDF unless the form asks for Word. Make it from a simple one-column layout (Google Docs, Word or LaTeX) so applicant tracking systems can read the text.
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