10 Physical Design Interview Questions and Answers for Freshers

• Import the netlist, libraries and timing constraints
• Floorplan (die size, IOs, macros)
• Power planning (rings, straps, rails)
• Placement of standard cells
• Clock tree synthesis
• Routing (global then detailed)
• Optimization and timing closure
• Signoff checks: STA, DRC, LVS, antenna, IR drop and electromigration
• Then GDSII for tape-out

Common mistake: Putting CTS before placement; forgetting power planning or signoff checks

Interviewer may ask next: Why is hold usually fixed after CTS and not before?

• Choose die and core size, aspect ratio and target utilization
• Place IO pins/pads
• Place macros (memories, IP) usually near the edges with channels between them and pins facing the core logic
• Add placement and routing blockages
• Plan the power grid
• A poor floorplan causes congestion and timing problems that later steps cannot fix

Common mistake: Placing macros in the middle with no channels; ignoring macro pin direction

Interviewer may ask next: How do you decide where to place memories with respect to the logic that uses them?

• CTS builds a tree of buffers/inverters that delivers the clock from its source to every flop
• goals: low skew between sinks, controlled insertion delay (latency), good transition times, and low power and area
• Before CTS the clock is ideal
• After CTS real skew is known, so timing is updated and hold is fixed
• Special rules like wider spacing (NDR) or shielding protect clock nets

Common mistake: Saying CTS only minimizes latency; forgetting that hold must be checked again after CTS

Interviewer may ask next: What is the difference between skew and insertion delay?

• utilization = area of standard cells (and macros) / core area
• Designs usually start around 60–75%
• Free space is needed for buffers added during optimization, the clock tree, routing tracks, hold fixing and later ECOs
• Too high utilization causes congestion and timing failures

Common mistake: Thinking 100% utilization is best because the chip is smaller

Interviewer may ask next: What problems would you see if you start a design at 90% utilization?

• DRC (design rule check) checks the layout against the foundry's manufacturing rules such as minimum width, spacing, enclosure and density
• LVS (layout versus schematic) extracts devices and connections from the layout and compares them with the netlist to make sure they match (no opens, shorts or missing devices)
• Both must be clean before tape-out

Common mistake: Swapping the meanings of DRC and LVS; thinking a DRC-clean layout is always correct

Interviewer may ask next: What would cause an LVS short, and how would you debug it?

• Congestion happens when an area needs more routing tracks than are available
• It causes detours, longer wires, DRC violations and timing problems
• fixes: better macro placement and wider channels, placement blockages or cell padding to spread dense logic, lower local utilization, reduce high pin-density cells, change the floorplan or pin placement

Common mistake: Only increasing utilization; ignoring congestion until detailed routing

Interviewer may ask next: How do you read a congestion map and find the cause?

• IR drop is the voltage loss in the power grid (current × resistance), so cells get less than full VDD and become slower
• It can be static (average current) or dynamic (switching bursts)
• EM is the slow movement of metal atoms caused by high current density over time, which can create opens or shorts
• fixes: wider or more power straps, more vias, decoupling capacitors, spreading high-activity cells

Common mistake: Saying IR drop only affects power, not timing; confusing EM with crosstalk

Interviewer may ask next: Why does dynamic IR drop matter more in high-speed designs?

• Crosstalk comes from coupling capacitance between neighbouring wires
• When an aggressor switches it can speed up or slow down a victim net that is switching (delay change), or put a glitch on a quiet victim (noise)
• Slow-down can cause setup failures and speed-up can cause hold failures
• fixes: more spacing, shielding with ground wires, upsizing the victim driver, changing layers, reducing parallel wire length

Common mistake: Thinking crosstalk only causes glitches, not delay changes

Interviewer may ask next: Why are clock nets often shielded or given extra spacing?

• During manufacturing, a long metal wire connected to a transistor gate can collect charge from plasma etching before the driver is connected
• This charge can damage the thin gate oxide
• Antenna rules limit the ratio of metal area to gate area
• fixes: break the wire and jump to a higher metal layer near the gate, add an antenna (reverse-biased) diode at the gate, or insert a buffer close to the gate

Common mistake: Saying antenna violations matter for the finished chip's normal operation; adding the diode at the driver instead of the gate

Interviewer may ask next: Why does jumping to a higher metal layer fix an antenna violation?

• Standard cells are library gates and flops with a fixed height that sit in rows
• Well tap cells connect the N-well to VDD and the substrate to VSS at regular spacing to prevent latch-up
• End-cap cells sit at the ends of rows to protect the cell edges and well boundaries
• Filler cells fill empty gaps in rows to keep wells and implants continuous
• Decap cells add local charge to reduce dynamic IR drop

Common mistake: Confusing tap cells with fillers; thinking fillers add logic

Interviewer may ask next: What is latch-up, and why does tap cell spacing matter?