35 Verilog Interview Questions and Answers for Freshers

• Wire is a net: it only connects things and must be driven continuously (assign, gate or port output)
• Reg is a variable: it holds the last value assigned inside an initial/always block
• Reg does NOT always mean a flip-flop, synthesis decides that from the coding style
• Default value: wire = z, reg = x

Common mistake: Saying reg always becomes a flip-flop; saying wire can be assigned inside always

Interviewer may ask next: Can a reg synthesize to pure combinational logic? Show an example.

• wire = z (nothing driving it)
• reg = x (unknown)
• integer = x
• In SystemVerilog 2-state types like bit/int start at 0

Common mistake: Saying everything starts at 0

Interviewer may ask next: Why can an uninitialised reg hide a reset bug in simulation?

• Integer is a signed 32-bit (at least) variable
• Reg is unsigned by default and its width is whatever you declare
• Both are 4-state
• Integer is mainly used for loop counters and testbench math

Common mistake: Saying integer is 2-state

Interviewer may ask next: What happens if you assign -1 to a 4-bit reg and display it?

Blocking: RHS evaluated and LHS updated immediately, next statement waits; Non-blocking: all RHS evaluated first, LHS updated together at the end of the time step (NBA region); use <= for sequential logic (clocked always), = for combinational logic; mixing them in one block causes confusion/races

Common mistake: Only saying 'blocking is sequential, non-blocking is parallel' without the evaluate/update explanation

Interviewer may ask next: Write a 3-stage shift register with both styles and tell me what each one synthesizes to.

With = : c reads the NEW b, so b and c both get a on the same edge: two parallel flops fed by a (synthesis can merge them into one); With <= : c gets the OLD b, so you get two flops in series (a 2-stage shift register)

Common mistake: Saying both give the same hardware

Interviewer may ask next: Which version would you use for a synchronizer and why?

With temp: tmp = a; a = b; b = tmp; Without temp in a clocked block: a <= b; b <= a; works because both RHS are sampled before update; arithmetic/XOR trick: a = a ^ b; b = a ^ b; a = a ^ b

Common mistake: Using a = b; b = a; with blocking (both end up equal)

Interviewer may ask next: Why does the non-blocking swap work but the blocking one fails?

• Continuous (assign) drives a net all the time and re-evaluates whenever any RHS signal changes
• Procedural assignment happens inside initial/always only when that statement executes, and the target must be a variable (reg/integer)
• Procedural continuous (assign/deassign, force/release) is a separate, mostly testbench-only feature

Common mistake: Mixing up procedural continuous assign with normal assign

Interviewer may ask next: Where would you ever use force/release?

Both override a signal's normal value until released; force/release works on nets and variables; assign/deassign only on variables; mostly used in testbenches to inject faults or bypass logic; not synthesizable; avoid in RTL

Common mistake: Saying they are synthesizable

Interviewer may ask next: How would you force an internal DUT signal from the testbench using a hierarchical path?

#5 a = b: wait 5 units, THEN read b and assign; a = #5 b: read b NOW, assign that old value after 5 units; intra-assignment with <= models transport delay and does not block the next statement

Common mistake: Saying they behave the same

Interviewer may ask next: What is the value of a at t=5 if b changes at t=2 in each case?

• Initial runs once starting at time 0
• Always repeats forever
• Both start at time 0 in parallel
• Initial is generally not synthesizable (some FPGA tools accept it for register init)
• Always is the main RTL construct

Common mistake: Saying initial blocks run in order of writing

Interviewer may ask next: If you have 3 initial blocks, which one executes first?

• Always is a module-level procedural block that starts at time 0
• Forever is a looping statement used INSIDE an initial/always/task
• Forever needs a timing control inside or simulation hangs
• Forever is testbench code

Common mistake: Saying they are identical

Interviewer may ask next: Write a clock generator using forever.

It lists the events that wake up an always block; for combinational logic every signal read must be in the list, otherwise simulation behaves like a latch while synthesis ignores the list, giving a simulation-synthesis mismatch; use always @(*) (or always_comb in SV)

Common mistake: Saying a missing signal only causes a warning and has no effect

Interviewer may ask next: Give an example where a missing signal in the list makes RTL sim differ from gate sim.

• function: returns one value, executes in zero time, no delays/events/waits, must have at least one input, can call other functions but not tasks
• task: can have zero or more inputs/outputs/inouts, can contain timing (#, @, wait), can call tasks and functions, no return value (in Verilog)

Common mistake: Saying a function can call a task

Interviewer may ask next: Can a function be called from a continuous assign? Can a task?

• By default Verilog tasks/functions are static: one shared copy of local variables
• Automatic gives each call its own stack-allocated variables
• Needed for recursion and for tasks called concurrently (e.g. from fork branches)

Common mistake: Not knowing static is the default

Interviewer may ask next: Write a recursive factorial function. What happens without automatic?

• Parameter can be overridden from outside the module, localparam cannot (it is a fixed internal constant, often derived from parameters)
• Override with #(.WIDTH(16)) during instantiation (preferred) or defparam (old style, avoid)

Common mistake: Not knowing defparam is discouraged

Interviewer may ask next: Why do teams ban defparam in RTL?

• Creates repeated or conditional hardware at elaboration time
• Generate-for with genvar for N instances (e.g. N-bit ripple adder from full adders)
• Generate-if/case to include logic based on a parameter
• Loop index must be genvar
• Give the block a name for hierarchical access

Common mistake: Confusing generate-for with a run-time for loop

Interviewer may ask next: Write a generate loop that instantiates 8 full adders.

• == is logical equality: if any bit is x or z the result is x
• === is case equality: compares x and z literally and always returns 0 or 1
• === is not synthesizable, used in testbenches

Common mistake: Saying === is synthesizable

Interviewer may ask next: What does (4'b10x0 == 4'b10x0) return? And with ===?

• case: exact match including x and z
• casez: z (and ?) in either expression treated as don't care
• casex: both x and z treated as don't care
• Casex is risky because an x on the select in simulation can match a wrong branch and hide bugs
• Prefer casez for priority/wildcard decoding

Common mistake: Saying casex is the safest

Interviewer may ask next: Write a 4-bit priority encoder with casez.

• full_case: tells synthesis all possible values are covered, so no latch
• parallel_case: tells synthesis items never overlap, so no priority logic
• They are synthesis directives only, simulation ignores them, so they can create simulation-synthesis mismatch
• better: add default and write non-overlapping items (or SV unique/priority)

Common mistake: Thinking the pragmas change simulation

Interviewer may ask next: How do SystemVerilog unique and priority case replace these?

• If-else-if chain naturally infers priority (first true condition wins)
• Case with mutually exclusive items infers a parallel mux
• Case with overlapping items (casez wildcards) behaves with priority in order of listing
• Synthesis optimises if conditions are provably exclusive

Common mistake: Saying case always gives a mux

Interviewer may ask next: Which one gives better timing for a 16:1 selection?

• $display prints immediately when executed and adds a newline
• $write same but no newline
• $strobe prints at the end of the current time step (after NBA updates), so shows final values
• $monitor prints every time any listed argument changes, only one active monitor at a time

Common mistake: Saying $display shows post-NBA values

Interviewer may ask next: Why does $display after a <= assignment show the old value?

First number is the time unit for delays (#1 = 1 ns); second is precision (smallest step = 1 ps); delays are rounded to the precision, so #0.4567 becomes 0.457 ns; precision must be <= unit

Common mistake: Swapping unit and precision

Interviewer may ask next: With `timescale 10ns/1ns, what is #0.45 rounded to?

• `define creates a global text macro, active from where it is defined across later files
• `include pastes a whole file at that point
• Parameter is a module-scoped constant that can be overridden per instance
• Macros are not scoped and can clash, so prefer parameters for widths

Common mistake: Thinking `define is local to a module

Interviewer may ask next: How do `ifdef/`ifndef help with simulation vs synthesis code?

Gate-level (primitives like and/or), dataflow (assign with operators), behavioral (always/initial), switch-level (nmos/pmos); RTL in practice mixes dataflow and behavioral; structural = connecting module instances

Common mistake: Leaving out structural/hierarchical instantiation

Interviewer may ask next: Write a 2:1 mux in all three main styles.

• Width mismatch: extra MSBs are truncated, or missing MSBs are zero-extended (sign-extended if signed), usually only a lint warning
• Unconnected output: the logic driving only that port is removed by synthesis since nothing uses it
• Unconnected input floats to z, so tie it

Common mistake: Saying the tool always errors out

Interviewer may ask next: Why should lint warnings for width mismatch never be ignored?

`timescale 1ns/1ps; 100 MHz period 10 ns: always #5 clk1 = ~clk1; 25 MHz period 40 ns: always #20 clk2 = ~clk2; initialise both to 0 in an initial block, otherwise ~x stays x

Common mistake: Forgetting to initialise the clock, so it stays x

Interviewer may ask next: How would you add a phase offset of 2 ns to clk2?

Use a mod-5 counter (0..4) on posedge; output high for counts 0,1,2 and low for 3,4 gives 3/5 = 60%; output must come from a flop to avoid glitches; frequency becomes clk/5

Common mistake: Trying to use # delays in RTL

Interviewer may ask next: How would you make a 50% duty divide-by-3 clock?

• Initial blocks (mostly), # delays (ignored), $display and other system tasks, forever without clock, fork/join, force/release, === and !==, real types, events used for testbench sync, file I/O
• Loops are OK only if bounds are constant

Common mistake: Saying for loops are not synthesizable

Interviewer may ask next: Is a while loop synthesizable?

• Simulation checks the behaviour of the code over time using an event-driven simulator
• Synthesis converts RTL into a gate-level netlist using a cell library under timing/area constraints
• Synthesis ignores delays and sensitivity lists, so code can simulate one way and synthesize another

Common mistake: Saying synthesis checks functionality

Interviewer may ask next: What is gate-level simulation and why do we still do it?

• Verilog: C-like, weakly typed, concise, more common in Indian/US ASIC teams
• VHDL: Ada-like, strongly typed, verbose, common in defence/FPGA/Europe
• Both describe hardware at RTL and gate level
• SystemVerilog extends Verilog for verification

Common mistake: Saying one cannot do something the other can for RTL

• #0 pushes the statement to the inactive region of the current time step, used historically to win a race
• It only moves the race, it does not fix it
• Proper fix is non-blocking assignments or clocking blocks

Common mistake: Saying #0 means no delay so it does nothing

• Active (blocking assigns, continuous assigns, RHS of NBAs, $display), Inactive (#0), NBA (non-blocking LHS updates), Monitor/Postponed ($monitor, $strobe)
• New events can loop back to Active
• SystemVerilog adds Preponed (sampling for assertions), Observed, Reactive (program block) regions

Common mistake: Putting $strobe in the active region

Interviewer may ask next: In which region does an assertion sample its values?

• Zero-duration steps inside one simulation time where events are processed in order
• Signal updates in one delta trigger evaluations in the next delta
• Simulation time does not move until no more events are pending

Common mistake: Saying delta is a tiny non-zero delay

• $display prints 0 because it runs in the active region before the NBA update
• $strobe would print 1 because it runs after NBA updates at end of time step

Common mistake: Answering 1 for $display

Interviewer may ask next: What does $monitor(a) print here?

Two processes read/write the same variable in the same time step and the result depends on execution order; example: two always @(posedge clk) blocks with blocking assigns where one reads what the other writes; fix: use non-blocking for sequential logic, one writer per variable, clocking blocks in testbench

Common mistake: Not giving a concrete example

Interviewer may ask next: How does a program block help avoid testbench-DUT races?