10 Digital Electronics Interview Questions for VLSI Freshers

• A latch is level-sensitive: it is transparent while enable is active and holds when it is not
• A flip-flop is edge-triggered: it captures input only at the clock edge
• A flip-flop can be built from two latches (master-slave)
• Latches make timing analysis harder
• Incomplete if/case statements in combinational RTL infer unwanted latches

Common mistake: Saying a latch is faster so it is always better; confusing which one is edge-triggered

Interviewer may ask next: Why do designers try to avoid latches in RTL, and where are latches still used on purpose?

• Moore outputs depend only on the current state
• Mealy outputs depend on the current state and the current inputs
• Mealy can react in the same cycle and often needs fewer states
• Mealy outputs can change (glitch) when inputs change and create combinational input-to-output paths
• Moore outputs are easier to register and time

Common mistake: Saying Mealy outputs depend only on inputs; saying Moore needs fewer states

Interviewer may ask next: Convert a simple Mealy machine to Moore: how does the number of states change?

• Any Boolean function can be made from NAND alone: NOT = NAND with both inputs tied, AND = NAND followed by NOT, OR = NAND of inverted inputs
• 2:1 mux Y = A·S' + B·S
• With NANDs: one NAND as inverter to make S', then N1 = NAND(A, S'), N2 = NAND(B, S), Y = NAND(N1, N2)
• Total 4 NAND gates

Common mistake: Using an extra NOT gate type; forgetting that S' must also be made from a NAND

Interviewer may ask next: Build an XOR gate from only NAND gates. How many do you need?

• Divide-by-2: a D flip-flop with Q-bar fed back to D toggles every edge, giving half the frequency with 50% duty
• Divide-by-3 with 50% duty: build a mod-3 counter on the rising edge, make an output that is high for 1.5 cycles by also using a flop on the falling edge, and OR (or AND) the rising-edge and falling-edge outputs
• A mod-3 counter alone gives 33% or 66% duty

Common mistake: Saying a mod-3 counter alone gives 50% duty; forgetting the falling-edge flop

Interviewer may ask next: Why are generated clocks from dividers declared in SDC with create_generated_clock?

• A hazard is a short wrong pulse at an output when an input changes, caused by unequal delays through different paths
• A static-1 hazard can be removed by adding the redundant consensus term found in the K-map
• In synchronous designs glitches settle before the clock edge so they are harmless if outputs are registered
• They matter for clocks, resets, asynchronous signals and clock gating

Common mistake: Thinking glitches always break synchronous logic; removing the redundant term during optimization

Interviewer may ask next: Why should a clock-gating enable not come straight from combinational logic?

• Binary to Gray: the MSB stays the same, every other bit G[i] = B[i+1] XOR B[i], i.e. G = B XOR (B >> 1)
• Gray to binary: B[MSB] = G[MSB], then B[i] = B[i+1] XOR G[i] working down from the MSB
• Consecutive Gray values differ in only one bit
• Used in asynchronous FIFO pointers, rotary encoders and low-power counters

Common mistake: XORing with the wrong neighbour; forgetting that Gray-to-binary must be done MSB first

Interviewer may ask next: Why is Gray code used for asynchronous FIFO pointers?

• A ring counter is a shift register with the last output fed back to the first input
• With n flops it has n states and one 1 circulating
• A Johnson (twisted ring) counter feeds back the inverted last output
• It has 2n states with n flops
• Its states can be decoded with 2-input gates without glitches
• Both need a proper reset or self-correction from illegal states

Common mistake: Saying a Johnson counter has 2^n states; forgetting the inverted feedback

Interviewer may ask next: What happens if a ring counter starts in an illegal state like all zeros?

• In a ripple counter each flop is clocked by the output of the previous one, so delays add up bit by bit, outputs settle at different times (glitchy decoded outputs) and the maximum speed is lower
• In a synchronous counter all flops share one clock and next-state logic decides which bits toggle, so all bits change together
• Synchronous counters are preferred in ASIC design and are easy to time with STA

Common mistake: Saying ripple counters are faster because they use less logic; using a ripple output as a clock without care

Interviewer may ask next: Why are ripple counters hard to handle in STA?

• A PMOS pulls the output up to VDD and an NMOS pulls it down to ground
• When the input is low the PMOS is on and the output is high, when the input is high the NMOS is on and the output is low
• Dynamic (switching) power ≈ α × C × V² × f
• Short-circuit power flows briefly when both transistors are on during a transition
• Leakage (static) power flows even when idle and grows with lower threshold voltages
• Lowering VDD cuts dynamic power by the square

Common mistake: Saying CMOS uses no power when idle; forgetting the V² term

Interviewer may ask next: Why do low-power designs use clock gating and multiple voltage domains?

• Mealy version needs 4 states: S0 (nothing matched), S1 (seen 1), S2 (seen 10), S3 (seen 101)
• S0: 1→S1, 0→S0
• S1: 0→S2, 1→S1
• S2: 1→S3, 0→S0
• S3: 1→output 1 and go to S1 (the last 1 starts a new match), 0→S2 (the ending 10 is a valid start)
• A Moore version needs a 5th state for 'detected'
• Explain overlap by finding the longest suffix that is also a prefix

Common mistake: Going back to S0 after a detection (that breaks overlapping); wrong transition from S3 on input 0

Interviewer may ask next: How would the design change for non-overlapping detection?