10 Static Timing Analysis (STA) Interview Questions and Answers

• Setup time = minimum time the data must be stable BEFORE the active clock edge
• Hold time = minimum time the data must stay stable AFTER the clock edge
• Both come from the flip-flop's library characterization
• A violation can make the flop capture a wrong value or go metastable

Common mistake: Mixing up before and after; saying hold violations can be fixed by slowing the clock

Interviewer may ask next: Which of the two violations can be fixed by lowering the clock frequency, and why?

• Setup slack = required time - arrival time
• Required (setup) = clock period + capture clock latency - setup time - clock uncertainty
• arrival = launch clock latency + clock-to-Q + maximum combinational delay
• Hold slack = arrival - required, with arrival = launch latency + clock-to-Q + minimum combinational delay and required = capture latency + hold time (+ uncertainty)
• Positive slack means the check passes, negative means a violation

Common mistake: Using the maximum path delay for the hold check; forgetting clock latency or uncertainty

Interviewer may ask next: Why does the setup check use the slowest path but the hold check use the fastest path?

• The hold check compares data launched by an edge with the capture on the same edge, so the clock period does not appear in the equation
• Changing frequency cannot fix hold
• Fix by adding delay on the fast data path (delay buffers/cells), or by reducing skew between launch and capture clocks
• Fix hold after CTS with real clock delays

Common mistake: Saying a slower clock fixes hold; adding delay on the clock path of the capture flop (that makes hold worse)

Interviewer may ask next: After you add hold buffers, what must you check again and why?

• skew = difference in clock arrival time between the capture flop and the launch flop
• Positive skew (capture clock arrives later) gives more time for setup but makes hold harder
• Negative skew helps hold but hurts setup
• Skew can be used on purpose (useful skew) to fix critical paths

Common mistake: Saying skew is always bad; getting the direction of the effect wrong

Interviewer may ask next: What is useful skew, and what is the risk of using it?

• False path: a path that can never be active in real operation (or between unrelated asynchronous clocks) so it is excluded from timing with set_false_path
• Multicycle path: data is allowed N clock cycles to arrive, set with set_multicycle_path N -setup
• The hold check must usually be moved back with set_multicycle_path N-1 -hold
• Wrong exceptions can hide real timing bugs

Common mistake: Forgetting the hold adjustment for a multicycle path; marking real paths false just to remove violations

Interviewer may ask next: Why should clock domain crossing paths be timed as false paths only when a proper synchronizer exists?

• STA checks the timing of every path using delays from libraries and parasitics, without test vectors
• It is fast and covers all paths but does not check function
• Dynamic timing simulation runs vectors on the netlist with SDF delays
• It checks function too but only for the patterns simulated and is slow

Common mistake: Saying STA finds functional bugs; saying gate-level simulation covers every path

Interviewer may ask next: When would you still run gate-level simulation even if STA is clean?

• Input port to register, register to register, register to output port, input port to output port (pure combinational)
• Start points are input ports and clock pins of sequential cells
• Endpoints are data (D) pins of sequential cells and output ports
• Each path is checked for setup and hold

Common mistake: Calling a Q pin an endpoint; forgetting input-to-output combinational paths

Interviewer may ask next: How do set_input_delay and set_output_delay help time the paths that go to ports?

• Reduce data path delay: upsize weak cells, use faster (low-Vt) cells, restructure or simplify logic, move logic before/after the register (retiming), pipeline the path
• Reduce wire delay with buffering or better placement
• Reduce load and fanout
• Use useful skew by delaying the capture clock
• Lowering the clock frequency is the last resort
• Re-check hold and power after every fix

Common mistake: Adding delay buffers on the data path (that is a hold fix); ignoring the effect of fixes on hold and power

Interviewer may ask next: Why do low-Vt cells speed up a path, and what is their cost?

• OCV: cells and wires on the same chip have slightly different delays because of process, voltage and temperature differences
• STA applies derates, making the launch/data path slower and the capture path faster for setup (pessimistic), and the reverse for hold
• AOCV/POCV give more accurate location- or statistics-based derates
• CRPR (clock reconvergence pessimism removal) removes the extra pessimism on the clock path that launch and capture share, because one wire cannot be fast and slow at the same time

Common mistake: Applying derates without removing common clock path pessimism; confusing OCV with different corners

Interviewer may ask next: What is the difference between a timing corner and OCV derating?

• It reserves margin for clock jitter and, before CTS, for the expected skew of the clock tree that does not exist yet
• It reduces the time available for setup and adds margin for hold
• After CTS the real skew is calculated, so uncertainty is usually reduced to jitter plus a small margin

Common mistake: Thinking uncertainty is only jitter; keeping a large pre-CTS skew estimate after CTS

Interviewer may ask next: How is a clock defined in SDC with create_clock, and what does a generated clock mean?