How to become a Physical Design (PD) engineer: a step-by-step roadmap for freshers

What to learn, in what order, which tools and projects, and what interviewers ask: a clear 15-week path from ECE student to physical design engineer.

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The roadmap

1. 1

   Get the basics strongWeeks 1–3

   • Digital design basics: flops, setup and hold, clocks. See digital electronics questions.
   • CMOS basics: how a MOSFET and an inverter work, delay, power and the layers of a chip (wells, poly, metals, vias).
   • Linux commands and basic TCL scripting. PD engineers script every day.
   • Read a gate-level netlist and understand what a standard cell library (.lib, .lef) contains.
2. 2

   Learn static timing analysisWeeks 3–6

   • Setup and hold, slack equations, clock skew and latency.
   • SDC constraints: create_clock, input/output delays, false paths and multicycle paths.
   • OCV, derates, corners and CRPR. Read a timing report line by line.
   • Practise with our STA interview questions.
3. 3

   Learn the PD flow step by stepWeeks 6–10

   • Floorplan: core size, utilization, IO and macro placement, blockages.
   • Power planning: rings, straps and rails; then placement and optimization.
   • Clock tree synthesis: skew, latency, transition; fix hold after CTS.
   • Routing: global and detailed routing, congestion and how to fix it.
4. 4

   Learn signoff checksWeeks 10–12

   • DRC and LVS: what they check and how to debug common errors.
   • Antenna rules, IR drop, electromigration and crosstalk.
   • Timing signoff across corners and ECOs to fix the last violations.
   • See physical design questions.
5. 5

   Run a full flow yourselfWeeks 12–15

   • Install OpenLane (or OpenROAD) and take a small design all the way to GDSII.
   • Change the clock period and utilization and see how timing and congestion change.
   • Open the layout in KLayout or Magic and look at the clock tree and power grid.
6. 6

   Build your portfolio and applyWeeks 15+

   • GitHub: your OpenLane runs with the config, reports (timing, area, power, DRC) and a short write-up of what you changed and why.
   • Be ready to explain every number in your timing report.
   • Practise answers out loud with the AI Interview Bot.
   • Apply to fresher jobs and ask for a referral.

Tools

Projects to put on your resume

Pick two or three and finish them well. A finished project you can explain beats five half-done ones. Put the code on GitHub with a short README and waveforms.

1. Counter or ALU through OpenLane to GDSIIBeginner
   Run the full flow, then explain the floorplan, the clock tree and the final timing report.
2. Timing closure experimentBeginner
   Tighten the clock period step by step and record where setup fails and what the tool changes to fix it.
3. UART or SPI controller with a macroIntermediate
   Add a small SRAM or hard macro, place it well, and compare congestion with a bad placement.
4. Power grid and IR drop studyIntermediate
   Change strap width and spacing and compare IR drop and routing resources.
5. Small RISC-V core to GDSIIAdvanced
   Close timing on a real core and document the ECOs and trade-offs you made.

Interview topics to prepare

• STA: setup/hold, slack, skew, exceptions, OCV — 10 questions
• Physical design: flow, floorplan, CTS, congestion, IR/EM, antenna, cells — 10 questions
• Digital and CMOS basics: 10 questions
• Expect: "Read this timing report", "How do you fix this hold violation?", "Why is this area congested?"

Tips that make a difference

• PD hiring loves people who can script. Learn TCL and basic Python or Perl for reports.
• Know your OpenLane run inside out: every interviewer will ask what you changed and why.
• Learn to read timing, congestion and IR reports, not only the commands that make them.
• Physical design and STA go together; many fresher roles are 'PD + STA'.
• See what PD pays freshers in our salary guide.

Other paths